IPC-Stelle: G11C 27/00 [Version 2006.01]

SymbolTypTitel
GSKSECTION G — PHYSICS
G11KLINFORMATION STORAGE
G11CUKLSTATIC STORES (information storage based on relative movement between record carrier and transducer G11B; semiconductor devices for storage H01L, e.g. H01L 27/108-H01L 27/115; pulse technique in general H03K, e.g. electronic switches H03K 17/00)
G11C 5/00HGRDetails of stores covered by group G11C 11/00
G11C 5/02UGR1
.Disposition of storage elements, e.g. in the form of a matrix array
G11C 5/04UGR2
. .Supports for storage elements; Mounting or fixing of storage elements on such supports
G11C 5/05UGR3
. . .Supporting of cores in matrix [2]
G11C 5/06UGR1
.Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 5/08UGR2
. .for interconnecting magnetic elements, e.g. toroidal cores
G11C 5/10UGR2
. .for interconnecting capacitors
G11C 5/12UGR1
.Apparatus or processes for interconnecting storage elements, e.g. for threading magnetic cores
G11C 5/14UGR1
.Power supply arrangements (auxiliary circuits for stores using semiconductor devices G11C 11/4063, G11C 11/413, G11C 11/4193; in general G05F, H02J, H02M) [5, 7]
G11C 7/00HGRArrangements for writing information into, or reading information out from, a digital store (G11C 5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C 11/4063, G11C 11/413, G11C 11/4193) [2, 5]
G11C 7/02UGR1
.with means for avoiding parasitic signals
G11C 7/04UGR1
.with means for avoiding disturbances due to temperature effects
G11C 7/06UGR1
.Sense amplifiers; Associated circuits (amplifiers per seH03F, H03K) [1, 7]
G11C 7/08UGR2
. .Control thereof [7]
G11C 7/10UGR1
.Input/output (I/O) data interface arrangements, e.g. I/O data control circuits, I/O data buffers (level conversion circuits in general H03K 19/0175) [7]
G11C 7/12UGR1
.Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines [7]
G11C 7/14UGR1
.Dummy cell management; Sense reference voltage generators [7]
G11C 7/16UGR1
.Storage of analogue signals in digital stores using an arrangement comprising analogue/digital (A/D) converters, digital memories and digital/analogue (D/A) converters [7]
G11C 7/18UGR1
.Bit line organisation; Bit line lay-out [7]
G11C 7/20UGR1
.Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory [7]
G11C 7/22UGR1
.Read-write (R-W) timing or clocking circuits; Read-write (R-W) control signal generators or management [7]
G11C 7/24UGR1
.Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells [7]
G11C 8/00HGRArrangements for selecting an address in a digital store (auxiliary circuits for stores using semiconductor devices G11C 11/4063, G11C 11/413, G11C 11/4193) [2, 5]
G11C 8/02UGR1
.using selecting matrix [2]
G11C 8/04UGR1
.using a sequential addressing device, e.g. shift register, counter (using first in first out (FIFO) registers for changing speed of digital data flow G06F 5/06; using last in first out (LIFO) registers for processing digital data by operating upon their order G06F 7/00) [5]
G11C 8/06UGR1
.Address interface arrangements, e.g. address buffers (level conversion circuits in general H03K 19/0175) [7]
G11C 8/08UGR1
.Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines [7]
G11C 8/10UGR1
.Decoders [7]
G11C 8/12UGR1
.Group selection circuits, e.g. for memory block selection, chip selection, array selection [7]
G11C 8/14UGR1
.Word line organisation; Word line lay-out [7]
G11C 8/16UGR1
.Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups [7]
G11C 8/18UGR1
.Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe (RAS) or column address strobe (CAS) signals [7]
G11C 8/20UGR1
.Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access [7]
G11C 11/00HGRDigital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (G11C 14/00-G11C 21/00 take precedence) [5]
G11C 11/02UGR1
.using magnetic elements
G11C 11/04UGR2
. .using storage elements having cylindrical form, e.g. rod, wire (G11C 11/12, G11C 11/14 take precedence) [2]
G11C 11/06UGR2
. .using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element
G11C 11/061UGR3
. . .using elements with single aperture or magnetic loop for storage, one element per bit, and for destructive read-out [2]
G11C 11/063UGR4
. . . .bit-organized, such as, 2L/2D-, 3D-organization, i.e. for selection of an element by means of at least two coincident partial currents both for reading and for writing [2]
G11C 11/065UGR4
. . . .word-organized, such as 2D-organization, or linear selection, i.e. for selection of all the elements of a word by means of a single full current for reading [2]
G11C 11/067UGR3
. . .using elements with single aperture or magnetic loop for storage, one element per bit, and for non-destructive read-out [2]
G11C 11/08UGR2
. .using multi-aperture storage elements, e.g. using transfluxors; using plates incorporating several individual multi-aperture storage elements (G11C 11/10 takes precedence; using multi-aperture plates in which each individual aperture forms a storage element G11C 11/06) [2]
G11C 11/10UGR2
. .using multi-axial storage elements
G11C 11/12UGR2
. .using tensors; using twistors, i.e. elements in which one axis of magnetisation is twisted
G11C 11/14UGR2
. .using thin-film elements
G11C 11/15UGR3
. . .using multiple magnetic layers (G11C 11/155 takes precedence) [2]
G11C 11/155UGR3
. . .with cylindrical configuration [2]
G11C 11/16UGR2
. .using elements in which the storage effect is based on magnetic spin effect
G11C 11/18UGR1
.using Hall-effect devices
G11C 11/19UGR1
.using non-linear reactive devices in resonant circuits [2]
G11C 11/20UGR2
. .using parametrons [2]
G11C 11/21UGR1
.using electric elements [2]
G11C 11/22UGR2
. .using ferroelectric elements [2]
G11C 11/23UGR2
. .using electrostatic storage on a common layer, e.g. Forrester-Haeff tubes (G11C 11/22 takes precedence) [2]
G11C 11/24UGR2
. .using capacitors (G11C 11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C 11/34, e.g. G11C 11/40) [2, 5]
G11C 11/26UGR2
. .using discharge tubes [2]
G11C 11/28UGR3
. . .using gas-filled tubes [2]
G11C 11/30UGR3
. . .using vacuum tubes (G11C 11/23 takes precedence) [2]
G11C 11/34UGR2
. .using semiconductor devices [2]
G11C 11/35UGR3
. . .with charge storage in a depletion layer, e.g. charge coupled devices [7]
G11C 11/36UGR3
. . .using diodes, e.g. as threshold elements [2]
G11C 11/38UGR4
. . . .using tunnel diodes [2]
G11C 11/39UGR3
. . .using thyristors [5]
G11C 11/40UGR3
. . .using transistors [2]
G11C 11/401UGR4
. . . .forming cells needing refreshing or charge regeneration, i.e. dynamic cells [5]
G11C 11/402UGR5
. . . . .with charge regeneration individual to each memory cell, i.e. internal refresh [5]
G11C 11/403UGR5
. . . . .with charge regeneration common to a multiplicity of memory cells, i.e. external refresh [5]
G11C 11/404UGR6
. . . . . .with one charge-transfer gate, e.g. MOS transistor, per cell [5]
G11C 11/405UGR6
. . . . . .with three charge-transfer gates, e.g. MOS transistors, per cell [5]
G11C 11/406UGR5
. . . . .Management or control of the refreshing or charge-regeneration cycles [5]
G11C 11/4063UGR5
. . . . .Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing [7]
G11C 11/4067UGR6
. . . . . .for memory cells of the bipolar type [7]
G11C 11/407UGR6
. . . . . .for memory cells of the field-effect type [5]
G11C 11/4072UGR7
. . . . . . .Circuits for initialization, powering up or down, clearing memory or presetting [7]
G11C 11/4074UGR7
. . . . . . .Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits [7]
G11C 11/4076UGR7
. . . . . . .Timing circuits (for regeneration management G11C 11/406) [7]
G11C 11/4078UGR7
. . . . . . .Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C 29/52) [7]
G11C 11/408UGR7
. . . . . . .Address circuits [5]
G11C 11/409UGR7
. . . . . . .Read-write (R-W) circuits [5]
G11C 11/4091UGR8
. . . . . . . .Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating [7]
G11C 11/4093UGR8
. . . . . . . .Input/output (I/O) data interface arrangements, e.g. data buffers (level conversion circuits in general H03K 19/0175) [7]
G11C 11/4094UGR8
. . . . . . . .Bit-line management or control circuits [7]
G11C 11/4096UGR8
. . . . . . . .Input/output (I/O) data management or control circuits, e.g. reading or writing circuits, I/O drivers, bit-line switches [7]
G11C 11/4097UGR8
. . . . . . . .Bit-line organisation, e.g. bit-line layout, folded bit lines [7]
G11C 11/4099UGR8
. . . . . . . .Dummy cell treatment; Reference voltage generators [7]
G11C 11/41UGR4
. . . .forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger [5]
G11C 11/411UGR5
. . . . .using bipolar transistors only [5]
G11C 11/412UGR5
. . . . .using field-effect transistors only [5]
G11C 11/413UGR5
. . . . .Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction [5]
G11C 11/414UGR6
. . . . . .for memory cells of the bipolar type [5]
G11C 11/415UGR7
. . . . . . .Address circuits [5]
G11C 11/416UGR7
. . . . . . .Read-write (R-W) circuits [5]
G11C 11/417UGR6
. . . . . .for memory cells of the field-effect type [5]
G11C 11/418UGR7
. . . . . . .Address circuits [5]
G11C 11/419UGR7
. . . . . . .Read-write (R-W) circuits [5]
G11C 11/4193UGR3
. . .Auxiliary circuits specific to particular types of semiconductor storage devices, e.g. for addressing, driving, sensing, timing, power supply, signal propagation (G11C 11/4063, G11C 11/413 take precedence) [7]
G11C 11/4195UGR4
. . . .Address circuits [7]
G11C 11/4197UGR4
. . . .Read-write (R-W) circuits [7]
G11C 11/42UGR2
. .using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
G11C 11/44UGR2
. .using super-conductive elements, e.g. cryotron [2]
G11C 11/46UGR1
.using thermoplastic elements
G11C 11/48UGR1
.using displaceable coupling elements, e.g. ferromagnetic cores, to produce change between different states of mutual or self-inductance
G11C 11/50UGR1
.using actuation of electric contacts to store the information (mechanical stores G11C 23/00; switches providing a selected number of consecutive operations of the contacts by a single manual actuation of the operating part H01H 41/00)
G11C 11/52UGR2
. .using electromagnetic relays
G11C 11/54UGR1
.using elements simulating biological cells, e.g. neuron
G11C 11/56UGR1
.using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency (counting arrangements comprising multi-stable elements of this type H03K 25/00, H03K 29/00) [2]
G11C 13/00HGRDigital stores characterised by the use of storage elements not covered by groups G11C 11/00, G11C 23/00, or G11C 25/00
G11C 13/02UGR1
.using elements whose operation depends upon chemical change (using electrochemical charge G11C 11/00)
G11C 13/04UGR1
.using optical elements
G11C 13/06UGR2
. .using magneto-optical elements (magneto-optics in general G02F) [2]
G11C 14/00HGRDigital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down [5]
G11C 15/00HGRDigital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores (in which information is addressed to a specific location G11C 11/00) [2]
G11C 15/02UGR1
.using magnetic elements [2]
G11C 15/04UGR1
.using semiconductor elements [2]
G11C 15/06UGR1
.using cryogenic elements [2]
G11C 16/00HGRErasable programmable read-only memories (G11C 14/00 takes precedence) [5]
G11C 16/02UGR1
.electrically programmable [5]
G11C 16/04UGR2
. .using variable threshold transistors, e.g. FAMOS [5]
G11C 16/06UGR2
. .Auxiliary circuits, e.g. for writing into memory (in general G11C 7/00) [5]
G11C 16/08UGR3
. . .Address circuits; Decoders; Word-line control circuits [7]
G11C 16/10UGR3
. . .Programming or data input circuits [7]
G11C 16/12UGR4
. . . .Programming voltage switching circuits [7]
G11C 16/14UGR4
. . . .Circuits for erasing electrically, e.g. erase voltage switching circuits [7]
G11C 16/16UGR5
. . . . .for erasing blocks, e.g. arrays, words, groups [7]
G11C 16/18UGR4
. . . .Circuits for erasing optically [7]
G11C 16/20UGR4
. . . .Initialising; Data preset; Chip identification [7]
G11C 16/22UGR3
. . .Safety or protection circuits preventing unauthorised or accidental access to memory cells [7]
G11C 16/24UGR3
. . .Bit-line control circuits [7]
G11C 16/26UGR3
. . .Sensing or reading circuits; Data output circuits [7]
G11C 16/28UGR4
. . . .using differential sensing or reference cells, e.g. dummy cells [7]
G11C 16/30UGR3
. . .Power supply circuits [7]
G11C 16/32UGR3
. . .Timing circuits [7]
G11C 16/34UGR3
. . .Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention [7]
G11C 17/00HGRRead-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards (erasable programmable read-only memories G11C 16/00; coding, decoding or code conversion, in general H03M) [2, 5]
G11C 17/02UGR1
.using magnetic or inductive elements (G11C 17/14 takes precedence) [2, 5]
G11C 17/04UGR1
.using capacitive elements (G11C 17/06, G11C 17/14 take precedence) [2, 5]
G11C 17/06UGR1
.using diode elements (G11C 17/14 takes precedence) [2, 5]
G11C 17/08UGR1
.using semiconductor devices, e.g. bipolar elements (G11C 17/06, G11C 17/14 take precedence) [5]
G11C 17/10UGR2
. .in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM [5]
G11C 17/12UGR3
. . .using field-effect devices [5]
G11C 17/14UGR1
.in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM [5]
G11C 17/16UGR2
. .using electrically-fusible links [5]
G11C 17/18UGR2
. .Auxiliary circuits, e.g. for writing into memory (in general G11C 7/00) [5]
G11C 19/00HGRDigital stores in which the information is moved stepwise, e.g. shift registers (counting chains H03K 23/00)
G11C 19/02UGR1
.using magnetic elements (G11C 19/14 takes precedence) [2]
G11C 19/04UGR2
. .using cores with one aperture or magnetic loop [2]
G11C 19/06UGR2
. .using structures with a number of apertures or magnetic loops, e.g. transfluxors [2]
G11C 19/08UGR2
. .using thin films in plane structure [2]
G11C 19/10UGR2
. .using thin films on rods; with twistors [2]
G11C 19/12UGR1
.using non-linear reactive devices in resonant circuits [2]
G11C 19/14UGR1
.using magnetic elements in combination with active elements, e.g. discharge tubes, semiconductor elements (G11C 19/34 takes precedence) [2, 7]
G11C 19/18UGR1
.using capacitors as main elements of the stages [2]
G11C 19/20UGR1
.using discharge tubes (G11C 19/14 takes precedence) [2]
G11C 19/28UGR1
.using semiconductor elements (G11C 19/14, G11C 19/36 take precedence) [2, 7]
G11C 19/30UGR1
.using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled [2]
G11C 19/32UGR1
.using super-conductive elements [2]
G11C 19/34UGR1
.using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency [7]
G11C 19/36UGR2
. .using semiconductor elements [7]
G11C 19/38UGR1
.two-dimensional, e.g. horizontal and vertical shift registers [7]
G11C 21/00HGRDigital stores in which the information circulates (stepwise G11C 19/00)
G11C 21/02UGR1
.using electromechanical delay lines, e.g. using a mercury tank
G11C 23/00HGRDigital stores characterised by movement of mechanical parts to effect storage, e.g. using balls; Storage elements therefor (storing by actuating contacts G11C 11/48)
G11C 25/00HGRDigital stores characterised by the use of flowing media; Storage elements therefor
G11C 27/00HGRElectric analogue stores, e.g. for storing instantaneous values
G11C 27/02UGR1
.Sample-and-hold arrangements (G11C 27/04 takes precedence; sampling electrical signals, in general H03K) [2, 4]
G11C 27/04UGR1
.Shift registers (charge coupled devices per seH01L 29/76) [4]
G11C 29/00HGRChecking stores for correct operation; Testing stores during standby or offline operation [1, 2006.01]
G11C 29/02UGR1
.Detection or location of defective auxiliary circuits, e.g. defective refresh counters [2006.01]
G11C 29/04UGR1
.Detection or location of defective memory elements [2006.01]
G11C 29/06UGR2
. .Acceleration testing [2006.01]
G11C 29/08UGR2
. .Functional testing, e.g. testing during refresh, power-on self testing (POST) or distributed testing [2006.01]
G11C 29/10UGR3
. . .Test algorithms, e.g. memory scan (MScan) algorithms; Test patterns, e.g. checkerboard patterns [2006.01]
G11C 29/12UGR3
. . .Built-in arrangements for testing, e.g. built-in self testing (BIST) [2006.01]
G11C 29/14UGR4
. . . .Implementation of control logic, e.g. test mode decoders [2006.01]
G11C 29/16UGR5
. . . . .using microprogrammed units, e.g. state machines [2006.01]
G11C 29/18UGR4
. . . .Address generation devices; Devices for accessing memories, e.g. details of addressing circuits [2006.01]
G11C 29/20UGR5
. . . . .using counters or linear-feedback shift registers (LFSR) [2006.01]
G11C 29/22UGR5
. . . . .Accessing serial memories [2006.01]
G11C 29/24UGR5
. . . . .Accessing extra cells, e.g. dummy cells or redundant cells [2006.01]
G11C 29/26UGR5
. . . . .Accessing multiple arrays (G11C 29/24 takes precedence) [2006.01]
G11C 29/28UGR6
. . . . . .Dependent multiple arrays, e.g. multi-bit arrays [2006.01]
G11C 29/30UGR5
. . . . .Accessing single arrays [2006.01]
G11C 29/32UGR6
. . . . . .Serial access; Scan testing [2006.01]
G11C 29/34UGR6
. . . . . .Accessing multiple bits simultaneously [2006.01]
G11C 29/36UGR4
. . . .Data generation devices, e.g. data inverters [2006.01]
G11C 29/38UGR4
. . . .Response verification devices [2006.01]
G11C 29/40UGR5
. . . . .using compression techniques [2006.01]
G11C 29/42UGR5
. . . . .using error correcting codes (ECC) or parity check [2006.01]
G11C 29/44UGR4
. . . .Indication or identification of errors, e.g. for repair [2006.01]
G11C 29/46UGR4
. . . .Test trigger logic [2006.01]
G11C 29/48UGR3
. . .Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access (DMA) or using auxiliary access paths (external testing equipment G11C 29/56) [2006.01]
G11C 29/50UGR2
. .Marginal testing, e.g. race, voltage or current testing [2006.01]
G11C 29/52UGR1
.Protection of memory contents; Detection of errors in memory contents [2006.01]
G11C 29/54UGR1
.Arrangements for designing test circuits, e.g. design for test (DFT) tools [2006.01]
G11C 29/56UGR1
.External testing equipment for static stores, e.g. automatic test equipment (ATE); Interfaces therefor [2006.01]
G11C 99/00HGRSubject matter not provided for in other groups of this subclass [2006.01]