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Dokument US020080067626A1 (Seiten: 11)

Bibliografische Daten Dokument US020080067626A1 (Seiten: 11)
INID Kriterium Feld Inhalt
54 Titel TI [EN] METHOD FOR FABRICATING A TRENCH STRUCTURE, AND A SEMICONDUCTOR ARRANGEMENT COMPRISING A TRENCH STRUCTURE
71/73 Anmelder/Inhaber PA INFINEON TECHNOLOGIES AUSTRIA, AT
72 Erfinder IN HIRLER FRANZ, DE ; KAUTZSCH THORALF, DE ; MAUDER ANTON, DE ; RUEB MICHAEL, AT ; SCHULZE HANS-JOACHIM, DE ; STRACK HELMUT, DE ; WILLMEROTH ARMIN, DE
22/96 Anmeldedatum AD 06.08.2007
21 Anmeldenummer AN 83415407
Anmeldeland AC US
Veröffentlichungsdatum PUB 20.03.2008
33
31
32
Priorität PRC
PRN
PRD
DE
102006037510
20060810
51 IPC-Hauptklasse ICM H01L 29/94 (2006.01)
51 IPC-Nebenklasse ICS H01L 21/76 (2006.01)
IPC-Zusatzklasse ICA
IPC-Indexklasse ICI
Gemeinsame Patentklassifikation CPC H01L 21/3247
H01L 21/76224
H10D 62/116
H10D 64/027
H10D 64/117
H10D 84/141
H10D 84/143
MCD-Hauptklasse MCM H01L 29/94 (2006.01)
MCD-Nebenklasse MCS H01L 21/76 (2006.01)
MCD-Zusatzklasse MCA
57 Zusammenfassung AB [EN] A semiconductor device, in which a first trench section is produced proceeding from a surface of a semiconductor body into the semiconductor body. A semiconductor layer is produced above the surface and above the first trench section. A further trench section is produced in the semiconductor layer in such a way that the first trench section and the further trench section form a continuous trench structure.
56 Entgegengehaltene Patentdokumente/Zitate,
in Recherche ermittelt
CT US000007157378B2
US020070243692A1
US020080230916A1
56 Entgegengehaltene Patentdokumente/Zitate,
vom Anmelder genannt
CT
56 Entgegengehaltene Nichtpatentliteratur/Zitate,
in Recherche ermittelt
CTNP
56 Entgegengehaltene Nichtpatentliteratur/Zitate,
vom Anmelder genannt
CTNP
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Sequenzprotokoll
Prüfstoff-IPC ICP H01L 21/762 T