| 54 |
Title |
TI |
[EN] Fabrication methodology for optoelectronic integrated circuits |
| 71/73 |
Applicant/owner |
PA |
OPEL SOLAR INC, US
;
UNIV CONNECTICUT, US
|
| 72 |
Inventor |
IN |
TAYLOR GEOFF W, US
|
| 22/96 |
Application date |
AD |
Jun 11, 2015 |
| 21 |
Application number |
AN |
201514736421 |
|
Country of application |
AC |
US |
|
Publication date |
PUB |
Jun 13, 2017 |
33
31
32 |
Priority data |
PRC
PRN
PRD |
|
| 51 |
IPC main class |
ICM |
H01L 29/66
(2006.01)
|
| 51 |
IPC secondary class |
ICS |
H01L 33/00
(2010.01)
H01L 33/02
(2010.01)
H01L 33/04
(2010.01)
|
|
IPC additional class |
ICA |
|
|
IPC index class |
ICI |
|
|
Cooperative patent classification |
CPC |
H10D 30/015
H10H 20/013
H10H 20/0137
H10H 20/062
H10H 20/811
H10H 20/812
H10H 20/814
H10H 20/8215
H10H 20/824
|
|
MCD main class |
MCM |
H01L 29/66
(2006.01)
|
|
MCD secondary class |
MCS |
H01L 33/00
(2010.01)
H01L 33/02
(2010.01)
H01L 33/04
(2010.01)
|
|
MCD additional class |
MCA |
|
| 57 |
Abstract |
AB |
[EN] A method of forming an integrated circuit employs a plurality of layers formed on a substrate including i) n-type modulation doped quantum well structure (MDQWS) structure with n-type charge sheet, ii) p-type MDQWS, iii) undoped spacer layer formed on the n-type charge sheet, iv) p-type layer(s) formed on the undoped spacer layer, v) p-type etch stop layer formed on the p-type layer(s) of iv), and vi) p-type layers (including p-type ohmic contact layer(s)) formed on the p-type etch stop layer. An etch operation removes the p-type layers of vi) for a gate region of an n-channel HFET with an etchant that automatically stops at the p-type etch stop layer. Another etch operation removes the p-type etch stop layer to form a mesa at the p-type layer(s) of iv) which defines an interface to the gate region of the n-channel HFET, and a gate electrode is formed on such mesa. |
| 56 |
Cited documents identified in the search |
CT |
US000006974696B2
US000006977954B2
US000007551826B2
US020120175681A1
|
| 56 |
Cited documents indicated by the applicant |
CT |
US000005804847A
US000006031243A
US000006479844B2
US000006841795B2
US000006849866B2
US000006853014B2
US000006870207B2
US000006873273B2
US000006954473B2
US000006995407B2
US000007332752B2
US020140050242A1
|
| 56 |
Cited non-patent literature identified in the search |
CTNP |
|
| 56 |
Cited non-patent literature indicated by the applicant |
CTNP |
“Development of Refractory Ohmic Contact Materials for Gallium Arsenide Compound Semiconductors”, Masanori Murakami, Science and Technology of Advanced Materials 3 (2002) pp. 1-27. 1;
“InXGa1—XAs Ohmic Contacts to n-Type GaAs with a Tungsten Nitride Barrier”, Chihiro J. Uchibori et al., Journal of Electronic Materials, vol. 26, No. 4, 1997. 1;
Selective Rie in BC13/SF6 Plasmas for GaAs Hemt Gate Recess Etching, Y.S. Lee et al., Department of Chemical and Petroleum Engineering, University of Kansas, 2000. 1;
U.S. Appl. No. 14/222,841, filed Mar. 24, 2014, Geoff W. Taylor. 1;
U.S. Appl. No. 60/376,238, filed Apr. 26, 2002, Geoff W. Taylor. 1
|
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Citing documents |
|
Determine documents
|
|
Sequence listings |
|
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|
Search file IPC |
ICP |
H01L 33/00
H01L 33/06
H01L 33/10
|
