| 54 |
Titel |
TI |
[EN] Memory control system for a non-volatile memory and control method |
| 71/73 |
Anmelder/Inhaber |
PA |
STICHTING IMEC NEDERLAND, NL
|
| 72 |
Erfinder |
IN |
AGELL CARLOS, NL
;
GEMMEKE TOBIAS, DE
;
PENDERS JULIEN, BE
|
| 22/96 |
Anmeldedatum |
AD |
22.12.2014 |
| 21 |
Anmeldenummer |
AN |
201414579827 |
|
Anmeldeland |
AC |
US |
|
Veröffentlichungsdatum |
PUB |
25.10.2016 |
33
31
32 |
Priorität |
PRC
PRN
PRD |
EP
13197379
20131216
|
| 51 |
IPC-Hauptklasse |
ICM |
G06F 3/06
(2006.01)
|
| 51 |
IPC-Nebenklasse |
ICS |
G06F 13/16
(2006.01)
|
|
IPC-Zusatzklasse |
ICA |
|
|
IPC-Indexklasse |
ICI |
|
|
Gemeinsame Patentklassifikation |
CPC |
G06F 1/3275
G06F 13/1668
G06F 3/0619
G06F 3/0625
G06F 3/0653
G06F 3/0659
G06F 3/0679
Y02D 10/00
|
|
MCD-Hauptklasse |
MCM |
G06F 3/06
(2006.01)
|
|
MCD-Nebenklasse |
MCS |
G06F 13/16
(2006.01)
|
|
MCD-Zusatzklasse |
MCA |
|
| 57 |
Zusammenfassung |
AB |
[EN] A memory control system for controlling read and write operations of a non-volatile memory, wherein the memory control system comprises a memory controller that is adapted to implement a write operation for writing at least one block of data to the memory as a sequence of memory write and validation cycles for part of all of the data. In one example, the number of cycles is a function of the amount of successfully written data per cycle and is thus variable in dependence on the success of the data writing. The system also includes a power management unit, which is adapted to authorize or prevent the memory controller from conducting the write operation at the level of the write cycles thereby to control the timing of power consumption resulting from the cycles of the write operation. |
| 56 |
Entgegengehaltene Patentdokumente/Zitate,
in Recherche ermittelt |
CT |
US020130275691A1
|
| 56 |
Entgegengehaltene Patentdokumente/Zitate,
vom Anmelder genannt |
CT |
EP000001818830A2
GB000002464495A
US000005930168A
US000007596707B1
US020090213679A1
US020120023348A1
US020120023351A1
US020120331207A1
US020120331282A1
|
| 56 |
Entgegengehaltene Nichtpatentliteratur/Zitate,
in Recherche ermittelt |
CTNP |
|
| 56 |
Entgegengehaltene Nichtpatentliteratur/Zitate,
vom Anmelder genannt |
CTNP |
European Search Report, European Patent Application 13197379.4 dated Jun. 12, 2014. 1;
Takeuchi, Ken, "Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)", IEEE Journal of Solid-State Circuits, vol. 44, No. 4, Apr. 2009, pp. 1227-1234. 1
|
|
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|
|
Sequenzprotokoll |
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Prüfstoff-IPC |
ICP |
G06F 3/06
|
