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Dokument US000009425795B2 (Seiten: 17)

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Bibliografische Daten Dokument US000009425795B2 (Seiten: 17)
INID	Kriterium	Feld	Inhalt
54	Titel	TI	[EN] Circuit and method for detection and compensation of transistor mismatch
71/73	Anmelder/Inhaber	PA	STICHTING IMEC NEDERLAND, NL
72	Erfinder	IN	ASHOUEI MARYAM, NL ; GEMMEKE TOBIAS, DE
22/96	Anmeldedatum	AD	05.03.2014
21	Anmeldenummer	AN	201414772834
	Anmeldeland	AC	US
	Veröffentlichungsdatum	PUB	23.08.2016
33 31 32	Priorität	PRC PRN PRD	EP 2014054229 05.03.2014
33 31 32	Priorität	PRC PRN PRD	EP 13158266 07.03.2013
51	IPC-Hauptklasse	ICM	H03K 19/003 (2006.01)
51	IPC-Nebenklasse	ICS	G01R 17/02 (2006.01) G11C 29/02 (2006.01) H03K 19/00 (2006.01)
	IPC-Zusatzklasse	ICA	G11C 29/50 (2006.01)
	IPC-Indexklasse	ICI
	Gemeinsame Patentklassifikation	CPC	G01R 17/02 G11C 2029/5002 G11C 29/021 G11C 29/028 H03K 19/0027 H03K 19/00384 H03K 2217/0018
	MCD-Hauptklasse	MCM	H03K 19/003 (2006.01)
	MCD-Nebenklasse	MCS	G01R 17/02 (2006.01) G11C 29/02 (2006.01) H03K 19/00 (2006.01)
	MCD-Zusatzklasse	MCA	G11C 29/50 (2006.01)
57	Zusammenfassung	AB	[EN] The present disclosure relates to a detection circuit formed as part of an integrated circuit. In one example, the detection circuit includes a signal generator configured to generate a reference signal, and an amplification circuit comprising a p-channel transistor and an n-channel transistor, wherein the amplification circuit is affected by a variability that also affects a functional circuit formed as part of the integrated circuit. The variability causes the p-channel transistor and the n-channel transistor to have different respective drive strengths. The amplification circuit is configured to receive the reference signal and to provide an amplified signal representative of a difference in the respective drive strengths, wherein the reference signal is more insensitive to the variability than the amplified signal. The present disclosure also relates to an integrated circuit and a method for detecting and compensating a transistor mismatch.
56	Entgegengehaltene Patentdokumente/Zitate, in Recherche ermittelt	CT	US000005397934A US000006529421B1 US000007532059B2 US000007564296B2 US020030080802A1 US020050280463A1 US020070018864A1 US020110012672A1 US020150016195A1
56	Entgegengehaltene Patentdokumente/Zitate, vom Anmelder genannt	CT	US000006466077B1 US000006653890B2 US000006731158B1 US000007548822B2 US020070045744A1 US020070085596A1 US020070236277A1
56	Entgegengehaltene Nichtpatentliteratur/Zitate, in Recherche ermittelt	CTNP
56	Entgegengehaltene Nichtpatentliteratur/Zitate, vom Anmelder genannt	CTNP	Gattiker, Anne et al., "Using Well/Substate Bias Manipulation to Enhance Voltage-Test-Based Defect Detection", 2011 IEEE International Test Conference (ITC), Sep. 20-22, 2011, pp. 1-6. 1; Ghosh, Amlan et al., "Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Nov. 15, 2012, pp. 1-10. 1; Ono, Goichi et al., "Threshold-Voltage Balance for Minimum Supply Operation", IEEE Journal of Solid-State Circuits, vol. 38, No. 5, May 2003, pp. 830-833. 1; PCT International Search Report and Written Opinion, PCT International Application No. PCT/EP2014/054229, dated Jun. 5, 2014. 1; Pu, Yu et al., "Vt Balancing and Device Sizing Towards High Yield of Sub-Threshold Static Logic Gates", Proc. ISLPED, Aug. 27-29, 2007, pp. 355-358. 1
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	Prüfstoff-IPC	ICP	G01R 17/02 G11C 29/02 G11C 29/50 H03K 19/003 H03K 19/00