Bibliografische Daten

Dokument US000008370409B2 (Seiten: 12)

Bibliografische Daten Dokument US000008370409B2 (Seiten: 12)
INID Kriterium Feld Inhalt
54 Titel TI [EN] Electronic computing circuit for operand width reduction for a modulo adder followed by saturation concurrent message processing
71/73 Anmelder/Inhaber PA GEMMEKE TOBIAS, US ; IBM, US ; MAEDING NICOLAS, DE ; PREISS JOCHEN, DE
72 Erfinder IN GEMMEKE TOBIAS, US ; MAEDING NICOLAS, DE ; PREISS JOCHEN, DE
22/96 Anmeldedatum AD 11.02.2008
21 Anmeldenummer AN 2888908
Anmeldeland AC US
Veröffentlichungsdatum PUB 05.02.2013
33
31
32
Priorität PRC
PRN
PRD
EP
07102221
20070213
51 IPC-Hauptklasse ICM G06F 7/00 (2006.01)
51 IPC-Nebenklasse ICS
IPC-Zusatzklasse ICA
IPC-Indexklasse ICI
Gemeinsame Patentklassifikation CPC G06F 7/499
G06F 7/727
MCD-Hauptklasse MCM G06F 7/00 (2006.01)
MCD-Nebenklasse MCS
MCD-Zusatzklasse MCA
57 Zusammenfassung AB [EN] A method for operand width reduction is described, wherein two N-bit input operands (A, B) of a bit width of N are processed and two M-bit output operands (A′, B′) of a reduced bit width of M are generated in a way, that a post-processing comprising an M-bit adder function followed by saturation to M bits performed on said two M-bit output operands (A′, B′) provides an M-bit result equal to an M-bit result of an N-bit modulo adder function of the two N-bit input operands (A, B), followed by a saturation to M bits. Further an electronic computing circuit (1, 5) is described performing said method. Additionally a computer system comprising such an electronic computing circuit is described.
56 Entgegengehaltene Patentdokumente/Zitate,
in Recherche ermittelt
CT US000006499046B1
56 Entgegengehaltene Patentdokumente/Zitate,
vom Anmelder genannt
CT
56 Entgegengehaltene Nichtpatentliteratur/Zitate,
in Recherche ermittelt
CTNP
56 Entgegengehaltene Nichtpatentliteratur/Zitate,
vom Anmelder genannt
CTNP
Zitierende Dokumente Dokumente ermitteln
Sequenzprotokoll
Prüfstoff-IPC ICP G06F 7/50
G06F 7/72