Bibliografische Daten

Dokument US000008266411B2 (Seiten: 18)

Bibliografische Daten Dokument US000008266411B2 (Seiten: 18)
INID Kriterium Feld Inhalt
54 Titel TI [EN] Instruction set architecture with instruction characteristic bit indicating a result is not of architectural importance
71/73 Anmelder/Inhaber PA GEMMEKE TOBIAS, DE ; IBM, US ; KALTENBACH MARKUS, DE ; MAEDING NICOLAS, DE
72 Erfinder IN GEMMEKE TOBIAS, DE ; KALTENBACH MARKUS, DE ; MAEDING NICOLAS, DE
22/96 Anmeldedatum AD 05.02.2009
21 Anmeldenummer AN 36616909
Anmeldeland AC US
Veröffentlichungsdatum PUB 11.09.2012
33
31
32
Priorität PRC
PRN
PRD


51 IPC-Hauptklasse ICM G06F 9/30 (2006.01)
51 IPC-Nebenklasse ICS
IPC-Zusatzklasse ICA
IPC-Indexklasse ICI
Gemeinsame Patentklassifikation CPC G06F 9/30076
G06F 9/30185
G06F 9/30192
G06F 9/3832
G06F 9/3838
G06F 9/384
G06F 9/3861
MCD-Hauptklasse MCM G06F 9/30 (2006.01)
MCD-Nebenklasse MCS
MCD-Zusatzklasse MCA
57 Zusammenfassung AB [EN] Instead of having a processor with an instruction set architecture (ISA) that includes fixed architected operands, an improved processor supports additional characteristic bits for computing instructions (e.g., a multiply-add, load/store instructions). Such additional bits for the certain instructions influence the processing of these instructions by the processor. Also, a new instruction is introduced for further usage of the proposed method. Typically these additional characteristic bits as well as the instruction can be automatically generated by compilers to provide relatively well-suited instruction sequences for the processor.
56 Entgegengehaltene Patentdokumente/Zitate,
in Recherche ermittelt
CT US000005557763A
US000005913925A
US000006092175A
US000006145074A
US000006314511B2
US020020087836A1
US020060101434A1
56 Entgegengehaltene Patentdokumente/Zitate,
vom Anmelder genannt
CT US000007284100B2
US000007281115B2
US000007197601B2
56 Entgegengehaltene Nichtpatentliteratur/Zitate,
in Recherche ermittelt
CTNP
56 Entgegengehaltene Nichtpatentliteratur/Zitate,
vom Anmelder genannt
CTNP A Comparison of Full and Partial Predicted Execution Support for ILP Processors, Scott A. Mahlke et al., Center for Reliable and High-Performance Computing, University of Illinois, Urbana-Champaign, IL 61801. 1;
Binary Floating-Point Unit Design: The Fused Multiply-Add Dataflow, Eric M. Schwarz., IBM Corp., MS:P310, 2455 South Road Poughkeepsie, NY, 12601. (Submitted by Author for publication in High-Performance Energy-efficient Microprocessor Design, http:www.ecampus.com/book/0387285946, Sep. 20, 2007, 17:49, as Chapter 8). 1;
IBM POWER6 Accelerators: VMX and DFU, L. Eisen, et al., IBM J. Res. & Dev., vol. 51, No. 6, Nov. 2007. 1;
Impact of Dynamic Allocation of Physical Register Banks for an SMT Processor, Norito Kato, et al., Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04), IEEE, Computer Society. 1;
Organization and Implementation of the Register-Renaming Mapper for Out-of-Order IBM POWER4 Processors, T.N. Buti, et al., IBM J. Res. & Dev., vol. 49, No. 1, Jan. 2005. 1
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