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A Comparison of Full and Partial Predicted Execution Support for ILP Processors, Scott A. Mahlke et al., Center for Reliable and High-Performance Computing, University of Illinois, Urbana-Champaign, IL 61801. 1; Binary Floating-Point Unit Design: The Fused Multiply-Add Dataflow, Eric M. Schwarz., IBM Corp., MS:P310, 2455 South Road Poughkeepsie, NY, 12601. (Submitted by Author for publication in High-Performance Energy-efficient Microprocessor Design, http:www.ecampus.com/book/0387285946, Sep. 20, 2007, 17:49, as Chapter 8). 1; IBM POWER6 Accelerators: VMX and DFU, L. Eisen, et al., IBM J. Res. & Dev., vol. 51, No. 6, Nov. 2007. 1; Impact of Dynamic Allocation of Physical Register Banks for an SMT Processor, Norito Kato, et al., Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04), IEEE, Computer Society. 1; Organization and Implementation of the Register-Renaming Mapper for Out-of-Order IBM POWER4 Processors, T.N. Buti, et al., IBM J. Res. & Dev., vol. 49, No. 1, Jan. 2005. 1
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