| 54 |
Titel |
TI |
[EN] Field-effect-controlled semiconductor component and method of fabricating a doping layer in a vertically configured semiconductor component |
| 71/73 |
Anmelder/Inhaber |
PA |
INFINEON TECHNOLOGIES AG, DE
|
| 72 |
Erfinder |
IN |
EISELE IGNAZ, DE
;
FINK CHRISTOPH, DE
;
HANSCH WALTER, DE
;
WERNER WOLFGANG, DE
|
| 22/96 |
Anmeldedatum |
AD |
11.12.2001 |
| 21 |
Anmeldenummer |
AN |
1399701 |
|
Anmeldeland |
AC |
US |
|
Veröffentlichungsdatum |
PUB |
07.12.2004 |
33
31
32 |
Priorität |
PRC
PRN
PRD |
DE
10061529
20001211
|
| 51 |
IPC-Hauptklasse |
ICM |
H01L 29/76
|
| 51 |
IPC-Nebenklasse |
ICS |
|
|
IPC-Zusatzklasse |
ICA |
|
|
IPC-Indexklasse |
ICI |
|
|
Gemeinsame Patentklassifikation |
CPC |
H10D 30/0221
H10D 30/603
H10D 30/668
H10D 62/307
H10D 62/393
H10D 62/605
|
|
MCD-Hauptklasse |
MCM |
|
|
MCD-Nebenklasse |
MCS |
H01L 21/336
(2006.01)
H01L 29/10
(2006.01)
H01L 29/36
(2006.01)
H01L 29/78
(2006.01)
|
|
MCD-Zusatzklasse |
MCA |
|
| 57 |
Zusammenfassung |
AB |
[EN] A field-effect-controllable semiconductor component has at least one source zone and at least one drain zone of a first conductivity type, and at least one body zone of a second conductivity type. The body zone is provided between the source zone and the drain zone. In each case at least a first and a second region of the second conductivity type are provided in a channel zone. The first region has a first doping concentration and the second region has a second doping concentration, which is lower than the first doping concentration. The combination of the two regions produces a semiconductor component threshold voltage greater than zero and the on resistance is lower than that merely due to a channel zone doped with the first or second doping concentration. |
| 56 |
Entgegengehaltene Patentdokumente/Zitate,
in Recherche ermittelt |
CT |
US000004395725A
US000004472727A
US000005013685A
US000005422510A
US000005438215A
US000005451533A
US000005475245A
US000005510635A
US000005536957A
US000005543654A
US000005569943A
US000005606184A
US000005714781A
US000005731611A
US000005751045A
US000005753958A
US000005760435A
US000005786620A
US000005793055A
US000005912488A
US000005945708A
US000005998833A
US000006184555B1
US020010000625A1
US020020063281A1
US020020117715A1
|
| 56 |
Entgegengehaltene Patentdokumente/Zitate,
vom Anmelder genannt |
CT |
DE000004309764C2
EP000001054450A2
US000004754310A
US000005216275A
US000005355008A
WO001997029518A1
|
| 56 |
Entgegengehaltene Nichtpatentliteratur/Zitate,
in Recherche ermittelt |
CTNP |
Muller et al. Device Electronics for Integrated Circuits, 1986, John Wiley & Sons, Second Edition, 443-454.* 0
|
| 56 |
Entgegengehaltene Nichtpatentliteratur/Zitate,
vom Anmelder genannt |
CTNP |
B. Jayant Baliga: "Power Semiconductor Devices", PWS Publishing Company, Boston, 1996, pp. 10, 11, 18, 19, 362 and 363. 1;
Jens Peer Stengl et al.: "Leistungs-MOS-FET-Praxis" [power MOSFET practice], Pflaum Verlag, Munich, 2ed., 1992, p. 44. 1;
V. Ramgopal Rao et al.: "Simulation, Fabrication and Characterization of High Performance Planar-Doped-Barrier Sub 100 nm Channel MOSFETs", Technical Digest IEDM, 1997, pp. 811-814. 1
|
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