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Entgegengehaltene Nichtpatentliteratur/Zitate,
vom Anmelder genannt |
CTNP |
A.S. Grove: "Physics and Technology of Semiconductor Devices" p 78-83 1967 Intel. 1;
Adrian Rusu, Contantin Bulucea: "Deep-Depletion Breakdown Voltage of Silicon-Dioxide/Silicon MOS Capacitors"v (p 201-205) No date. 1;
Akio Nakagawa, David H. Navon: "A Time- and Temperature-Dependent 2-D Simulation of the GTO Thyristor Turn-Off Process" (p 1156-1163) 1984 IEEE. 1;
Article "Power Semiconductors Proliferate" published in Electronics Products magazine re: Infineon CoolMOS products and IR CoolMOS- equivalent devices. Jul. 1999 Ek. Products. 1;
Article by Xing-Bi Chen presented at 2German-Chinese Electronics Week Congress, Shanghai, China 1991. 1;
Article from Acta Electronica Sinica, Mar. 1986, "A Novel InGaAs Phototransistor by CaO Emitter" (in Chinese) (p 35-39). 1;
Article from Chinese Journal of Semiconductors, May 1988 (p 255-260). 1;
B. Jayant Baliga, Sorab K. Ghandi: "Analytical Solutions for the Breakdown Voltage of Abrupt Cylindrical and Spherical Junctions" (p 739-744) 1976 SSE. 1;
B. Jayant Baliga: "Epitaxial Silicon Technology" 1986. 1;
B. Jayant Baliga: Modern Power Devices (Entire text, especially excerpt, p. 182-192, 338-339) 1987 GE. 1;
B.J. Baliga, M.S. Adler, R.P. Love et al: "Insulated Gate Transistor: A New Three-Terminal MOS-Controlled Bipolar Power Device" (excerpt) (p 1394-1402) 1984 IEEE. 1;
Board, Kenneth: "The Optimization of On-Resistance in Vertical DMOS Power Devices with Linear and Hexagonal Surface Geometries" 1984 IEEE. 1;
C. Frank Wheatley Jr., Gary M. Dolny: "COMFET-The Ultimate Power Device; A General Study of Power Devices" (p 121-128) Nov. 1985 SST. 1;
C. Hu article, "Optimum Doping Profile of Power MOSFETS Epitaxial Layer" 1979 IEEE. 1;
Chen Xingbi, Li Zhaoji, Jiang Xu: "Two-Dimensional Numerical Analysis of High-voltage Semiconductor Electric Fields" May 1988 Chinese J. Semi. 1;
Chen Xingbi, Li Zhaoji, Li Zhongmin: "Breakdown Voltage of Cylindrical Boundary Abrupt Junctions" (p 463-465) Jun. 1989 Chinese J. of Semi. 1;
Chen article, "Optimization of the Specific On-Resistance of the CoolMOS," published by IEEE Transactions on Electron Devices 2001 IEEE. 1;
Chen article, "Theory of a Novel Voltage Sustaining (CB) Layer for Power Devices" (from Chinese Journal of Electronics) Mar. 1998. 1;
Chenming Hu article, "Optimum Doping Profile for Minimum Ohmic Resistance and High-Breakdown Voltage" No date. 1;
Chenming Hu, Min-Hwa Chi, Vikram M. Patel: "Optimum Designs of Power MOSFET'S" (p 1693-1700) 1984 IEEE. 1;
Chenming Hu: "A Parametric Study of Power MOSFETS" ( p 988-998) 1979 IEEE. 1;
Claus Geisler, "Birth of the Cool in MOS" May 1998 Components. 1;
Daisuke Ueda, Hiromitsu Takagi, Gota Kano: An Ultra-Low On-Resistance Power MOSFET Fabricated by Using a Fully Self-Aligned Process No Date. 1;
Deboy et al. article, "A New Generation of High Voltage MOSFETS breaks the Limit Line of Silicon" published by IEEE (2nd, color copy added, 2nd set of Bates ranges correspond) No date. 1;
G. Bell, W. Ladenhauf: "SIPMOS Technology, an Example of VLSI Precision Realized with Standard LSI for Power Transistors" (p 190-194) 1980. 1;
H.R. Chang, F.W. Holroyd: "High Voltage Power MOSFET'S with a Trench-Gate Structure" (p 381-387) Sep. 1989 SSE. 1;
H.R. Chang, R.D. Black, V.A.K. Temple, Wirojana Tantraporn, B. Jayant Baliga: IEEE Transaction, Nov. 1987; Self-Aligned UMOSFTS'S with a Specific On-Resistance of 1m cm2 (p. 2329-2334). 1;
IEDM Technical Digest excerpt (p. 239, 241) 1979. 1;
J.A. Appel, H.M.J. Vaes: "High Voltage Thin Layer Devices (Resurf Devices)" (p 1384-1387) 1979 IEEE. 1;
J.P. Stengl, H. Strack, J. Tihanyi: "Power MOS Transistors for 1000 V Blocking Voltage" (p 422-425) 1981 IEEE. 1;
Jerry G. Fossum, Robert J. McDonald: "Charge Control Analysis of the COMFET Turn-Off Transient" (p 1377-1382) 1986 IEEE. 1;
Lai, et al.; "Characteristics and Utilization of a New Class of Low On-Resistance MOS-Gated Power Device" (1999) IEEE. 1;
Li Zhoaji, Yu Hongquan, Chen Xingbi: "Temperature Distribution of Full Thermal Path of VDMOS" (p 435-440) Jun. 1990 Chinese J. of Semi. 1;
Lorenz et al. article, "Drastic Reduction of On-Resistance with CoolMOS" in PCIM Europe May 1998. 1;
Lorenz et al. article, "Improved MOSFET An Important Milestone Toward a New Power MOSFET Generation" featured in PCIM Sep. 1998 PCIM. 1;
Min-hwa Chi, Chenming Hu: "Some Issues of Power MOSFETS" (p 392-393) 1982 IEEE. 1;
P.L. Hower, T.M.S. Heng, C. Huang: "Optimum Design of Power MOSFETS" (p 980-984) 1983 IEEE. 1;
R. Stengl, U. Gsele: "Variation of Lateral Doping-A New Concept to Avoid High Voltage Breakdown of Planar Junctions" (p 154-157) 1985 IEEE. 1;
Richard A. Blanchard: "Optimization of Discrete High Power MOS Transistors" 1981. 1;
Richard F. David: "Computerized Thermal Analysis of Hybrid Circuits" 27th Electronics Components Conference, May 16-18 1977 (p 324-332). 1;
S.C. Sun, James D. Plummer: "Modeling of the On-Resistance of LDMOS, VDMOS, and VMOS Power Transistors" (p 356-357) 1980 IEEE. 1;
Sel Colak: "Effects of Drift Region Parameters n the same properties of Power LDMOST" (p 1455-1466) 1981 IEEE. 1;
Steve Bush, "Five-fold resistance cut for high-voltage FETs" Jul. 1998 Ele. Wk. 1;
Takeaki Okabe, Isao Yoshida, Skikayuki Ochi: "A Complementary Pair of Planar-Power MOSFETS" (p 334-339) 1980 IEEE. 1;
Tihanyi "A Qualitative Study of the DC performance of SIPMOS Transistors" p 181-190 1980. 1;
Tihanyi and Krauss, SIPMOS, Elektronik 1980, p. 61-64. 1;
Victor K. Temple, Robert P. Love, Peter V. Gray: "A 600-Volt MOSFET Designed for Low On-Resistance" (p 343-349) 1980 IEEE. 1;
Victor K. Temple: "Ideal FET Doping Profile" (p 619-626) 1983 IEEE. 1;
Victor K. Temple: "Increased Avalanche Breakdown Voltage and Controlled Surface Electric Fields Using a Junction Termination Extension (JTE) Technique" (p 954-957) 1983 IEEE. 1;
Vinson C. Alwin, David H. Navon, Luke J. Turgeon: "Time-Dependent Carrier Flow in a Transistor Structure Under Nonisothermal Conditions" (p 1297-1304) Nov. 1977 IEEE. 1;
William A. Lane, C. Andre T. Salama: "Epitaxial VVMOS Power Transistors" (p 349-355) 1980 IEEE. 1;
Wirojana Tantraporn, Victor A.K. Temple: "Multiple-Zone Single-Mask Junction Termination Extension-A High-Yield Near-Ideal Breakdown Voltage Technology" (p 220-2210) 1987 IEEE. 1;
X.B. Chen et al. "High voltage sustaining structure with enbedded oppositely doped regions" May 1999 IEE. 1;
X.B. Chen et al., "Theory of a novel voltage-sustaining layer for power devices" (from Microelectronics Journal) 1998 Microele, J. 1;
X.B. Chen, P.A Mawby, K. Board et al, "Theory of a Novel Voltage-Sustaining Layer for Power Devices" (from Microelectronics Journal) 1998. 1;
X.B. Chen, Z.Q. Song, Z.J. Li: "Optimization of the Drift Region of Power MOSFET'S with Lateral Structures and Deep Junctions" (p 2344-2350) 1987 IEEE. 1;
Xing Bi Chen & Johnny K.O. Sin "A Novel High Voltage Sustaining Structure with Buried Oppositely Doped Regions" 2000 IEEE. 1;
Zahir Parpia, C. Andre T. Salama, Robert A. Hadaway, "A CMOS-Compatible High-Voltage IC Process" (p 1687-1694) 1988 IEEE. 1;
Zhang Bo, Chen Xingbi, Li Zhaoji: "Two Dimensional Electric Field Analysis of JTE Junctions" (p. 626-632) Oct. 1993 Chinese J. of Semi. 1
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