Bibliografische Daten

Dokument US000005723956A (Seiten: 8)

Bibliografische Daten Dokument US000005723956A (Seiten: 8)
INID Kriterium Feld Inhalt
54 Titel TI [EN] Low cost electronic ultracapacitor interface technique to provide load leveling of a battery for pulsed load or motor traction drive applications
71/73 Anmelder/Inhaber PA GEN ELECTRIC, US
72 Erfinder IN DEDONCKER RIK WIVINA ANNA ADEL, US ; KING ROBERT DEAN, US
22/96 Anmeldedatum AD 28.05.1996
21 Anmeldenummer AN 65447696
Anmeldeland AC US
Veröffentlichungsdatum PUB 03.03.1998
33
31
32
Priorität PRC
PRN
PRD


51 IPC-Hauptklasse ICM H02M 7/53
51 IPC-Nebenklasse ICS H02P 7/01
IPC-Zusatzklasse ICA
IPC-Indexklasse ICI
Gemeinsame Patentklassifikation CPC B60L 2210/20
B60L 50/40
H02J 7/34
H02M 1/14
Y02T 10/70
Y02T 10/72
MCD-Hauptklasse MCM
MCD-Nebenklasse MCS B60L 11/00 (2006.01)
H02J 7/34 (2006.01)
H02M 1/14 (2006.01)
MCD-Zusatzklasse MCA
57 Zusammenfassung AB [EN] A battery load leveling arrangement for an electrically powered system in which battery loading is subject to intermittent high current loading utilizes a passive energy storage device and a diode connected in series with the storage device to conduct current from the storage device to the load when current demand forces a drop in battery voltage. A current limiting circuit is connected in parallel with the diode for recharging the passive energy storage device. The current limiting circuit functions to limit the average magnitude of recharge current supplied to the storage device. Various forms of current limiting circuits are disclosed, including a PTC resistor coupled in parallel with a fixed resistor. The current limit circuit may also include an SCR for switching regenerative braking current to the device when the system is connected to power an electric motor.
56 Entgegengehaltene Patentdokumente/Zitate,
in Recherche ermittelt
CT US000005047913A
US000005260637A
US000005373195A
US000005591212A
56 Entgegengehaltene Patentdokumente/Zitate,
vom Anmelder genannt
CT
56 Entgegengehaltene Nichtpatentliteratur/Zitate,
in Recherche ermittelt
CTNP Design Methodologies For Soft Switched Inverters; D.M. Divan, G. Venkataramanan, R.W. DeDoncker; 1988 IEEE pp. 758 766, 88CH2565. 0
56 Entgegengehaltene Nichtpatentliteratur/Zitate,
vom Anmelder genannt
CTNP
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Sequenzprotokoll
Prüfstoff-IPC ICP H02M 5/45 C