| 54 |
Title |
TI |
[DE] PARALLELSCHALTEN VON HALBLEITERSCHALTEINRICHTUNGEN, INSBESONDERE IN EINEM FLUGZEUG
[EN] PARALLELING SEMICONDUCTOR SWITCH DEVICES, ESPECIALLY IN AN AIRCRAFT
[FR] MISE EN PARALLÈLE DE DISPOSITIFS DE COMMUTATION À SEMI-CONDUCTEUR, EN PARTICULIER DANS UN AVION |
| 71/73 |
Applicant/owner |
PA |
AIRBUS SAS, FR
|
| 72 |
Inventor |
IN |
GALEK MAREK, DE
;
KAPAUN FLORIAN, DE
|
| 22/96 |
Application date |
AD |
Nov 29, 2023 |
| 21 |
Application number |
AN |
23213100 |
|
Country of application |
AC |
EP |
|
Publication date |
PUB |
Jun 4, 2025 |
33
31
32 |
Priority data |
PRC
PRN
PRD |
|
| 51 |
IPC main class |
ICM |
H03K 17/12
(2006.01)
|
| 51 |
IPC secondary class |
ICS |
H02M 1/088
(2006.01)
H03K 17/13
(2006.01)
|
|
IPC additional class |
ICA |
|
|
IPC index class |
ICI |
|
|
Cooperative patent classification |
CPC |
H02M 1/088
H03K 17/122
H03K 17/133
H03K 2217/0036
|
|
MCD main class |
MCM |
H03K 17/12
(2006.01)
|
|
MCD secondary class |
MCS |
H02M 1/088
(2006.01)
H03K 17/13
(2006.01)
|
|
MCD additional class |
MCA |
|
| 57 |
Abstract |
AB |
[EN] For enabling paralleling a low number of semiconductors or modules, especially for aircraft applications, in a simplified, reliable way with minimal additional effort, the invention provides an operation method for a semiconductor switch arrangement (18) comprising a first semiconductor switch device (32.1) and a second semiconductor switch device (32.2) connected in parallel to each other between common nodes (N1, N2), the method comprising alternatively conducting a first switching period (SP1) and a second switching period (SP2), wherein the first switching period (SP1) comprises turning on the first switching device (32.1) to take the whole current (IL) between the common nodes (N1, N2) first and then turning on the second switching device (32.2) at zero voltage between the common nodes (N1, N2), and wherein the second switching period (SP2) comprises turning on the second switching device (32.2) to take the whole current (IL) between the common nodes first and then turning on the first switching device (32.1) at zero voltage between the common nodes (N1, N2). |
| 56 |
Cited documents identified in the search |
CT |
EP000004064564A1
JP0000S5465351A
KR000102403150B1
US000005399908A
US020160218621A1
|
| 56 |
Cited documents indicated by the applicant |
CT |
|
| 56 |
Cited non-patent literature identified in the search |
CTNP |
|
| 56 |
Cited non-patent literature indicated by the applicant |
CTNP |
"Edition", INFINEON TECHNOLOGIES AG, article "Paralleling power MOSFETs in high current applications -Effect of MOSFET parameter mismatch on current and power dissipation imbalance" 1;
"Hybrid and electric flight", AIRBUS, 15 November 2023 (2023-11-15), Retrieved from the Internet 1;
"Semiconductor Components Industries", May 2021, LLC, article "Paralleling Power MOSFETs for Switching Applications" 1;
WIKIPEDIA, ELECTRIC AIRCRAFT, 15 November 2023 (2023-11-15) 1;
WIKIPEDIA, POWER ELECTRONICS, 15 November 2023 (2023-11-15), Retrieved from the Internet 1
|
|
Citing documents |
|
Determine documents
|
|
Sequence listings |
|
|
|
Search file IPC |
ICP |
H03K 17/12
H03K 17/13
|
