Bibliographic data

Document EP000001217657A1 (Pages: 13)

Bibliographic data Document EP000001217657A1 (Pages: 13)
INID Criterion Field Contents
54 Title TI [DE] Verfahren zur Herstellung eines vergrabenen Kontaktstreifens in einer DRAM-Zelle
[EN] Method of forming a buried strap in a dram cell
[FR] Procédé de fabriquer un ruban enterré dans une cellule DRAM
71/73 Applicant/owner PA SEMICONDUCTOR 300 GMBH & CO KG, DE
72 Inventor IN DRABE CHRISTIAN, DE ; ZEHNER SIGURD, DE
22/96 Application date AD Dec 20, 2000
21 Application number AN 00128017
Country of application AC EP
Publication date PUB Jun 26, 2002
33
31
32		 Priority data PRC
PRN
PRD

51 IPC main class ICM H01L 21/8242
51 IPC secondary class ICS
IPC additional class ICA
IPC index class ICI
Cooperative patent classification CPC H10B 12/038
MCD main class MCM
MCD secondary class MCS H10B 12/00 (2023.01)
MCD additional class MCA
57 Abstract AB [EN] The present invention refers to the field of dynamic random access memories (DRAMs), and, in particular, to a method for making an electrical connection between a trench storage capacitor and an access transistor. The method of the present invention comprises the steps of preparing said semiconductor substrate, providing at least one isolating layer on said substrate, providing a deep trench (2) in said semiconductor substrate, forming a trench capacitor in a lower part of said deep trench, said trench capacitor having a trench center electrode (15) surrounded by an isolating material, filling said trench with a conductive material, the lower part of said conductive material being isolated from said semiconductor substrate by an isolating collar (4), defining an active area of said DRAM cell, said active area being adjacent to one side of said deep trench, forming a transistor in said active area with an electrode extending to make electrical contact with said conductive material in said deep trench (2), wherein the uppermost part of said conductive material in said trench, said uppermost part being at the same level as the isolating layer, is recessed to form a buried strap (5) after lithographically defining said active area. <IMAGE>
56 Cited documents identified in the search CT US000005389559A
56 Cited documents indicated by the applicant CT
56 Cited non-patent literature identified in the search CTNP "INTEGRATABLE RECESS 2 PROCESS FOR MEMORY STRUCTURES", IBM TECHNICAL DISCLOSURE BULLETIN,US,IBM CORP. NEW YORK, vol. 34, no. 4B, 1 September 1991 (1991-09-01), pages 291 - 292, XP000256682, ISSN: 0018-8689 0
56 Cited non-patent literature indicated by the applicant CTNP
Citing documents Determine documents
Sequence listings
Search file IPC ICP H01L 27/108 G