| 54 |
Title |
TI |
[DE] ZEITANZEIGEANORDNUNG
[EN] Analogue time display for electronic timepiece - uses groups of display elements associated with multi-stage buffer registers |
| 71/73 |
Applicant/owner |
PA |
BINNINGER DIETER ING GRAD
|
| 72 |
Inventor |
IN |
BINNINGER DIETER ING GRAD
|
| 22/96 |
Application date |
AD |
Apr 26, 1977 |
| 21 |
Application number |
AN |
2718535 |
|
Country of application |
AC |
DE |
|
Publication date |
PUB |
Nov 2, 1978 |
33
31
32 |
Priority data |
PRC
PRN
PRD |
|
| 51 |
IPC main class |
ICM |
G04C 17/00
|
| 51 |
IPC secondary class |
ICS |
|
|
IPC additional class |
ICA |
|
|
IPC index class |
ICI |
|
|
Cooperative patent classification |
CPC |
G04G 9/02
|
|
MCD main class |
MCM |
|
|
MCD secondary class |
MCS |
G04G 9/02
(2006.01)
|
|
MCD additional class |
MCA |
|
| 57 |
Abstract |
AB |
[EN] The analogue time display for an electronic timepiece comprises a gp. of 4 minute display elements, a gp. of 11 5-minute display elements, a gp. of 4 hr. display elements and a gp. of 2 or 4 5-hr. display elements. The display element gps. are associated with an equal number of buffer registers, with each element of each gp. coupled to a respective stage of the respective buffer register, for energising the elements in sequence. An AND gate is coupled to the second or last stage of the third buffer register to the output of the last stage of the fourth buffer register and to the first stage of the first buffer register. The output of the AND gate is coupled to the reset input of third and fourth buffer registers. |
| 56 |
Cited documents identified in the search |
CT |
|
| 56 |
Cited documents indicated by the applicant |
CT |
|
| 56 |
Cited non-patent literature identified in the search |
CTNP |
|
| 56 |
Cited non-patent literature indicated by the applicant |
CTNP |
|
|
Citing documents |
|
Determine documents
|
|
Sequence listings |
|
|
|
Search file IPC |
ICP |
G04G 9/08
|
