Bibliographic data

Document US020080067626A1 (Pages: 11)

Bibliographic data Document US020080067626A1 (Pages: 11)
INID Criterion Field Contents
54 Title TI [EN] METHOD FOR FABRICATING A TRENCH STRUCTURE, AND A SEMICONDUCTOR ARRANGEMENT COMPRISING A TRENCH STRUCTURE
71/73 Applicant/owner PA INFINEON TECHNOLOGIES AUSTRIA, AT
72 Inventor IN HIRLER FRANZ, DE ; KAUTZSCH THORALF, DE ; MAUDER ANTON, DE ; RUEB MICHAEL, AT ; SCHULZE HANS-JOACHIM, DE ; STRACK HELMUT, DE ; WILLMEROTH ARMIN, DE
22/96 Application date AD Aug 6, 2007
21 Application number AN 83415407
Country of application AC US
Publication date PUB Mar 20, 2008
33
31
32
Priority data PRC
PRN
PRD
DE
102006037510
20060810
51 IPC main class ICM H01L 29/94 (2006.01)
51 IPC secondary class ICS H01L 21/76 (2006.01)
IPC additional class ICA
IPC index class ICI
Cooperative patent classification CPC H01L 21/3247
H01L 21/76224
H01L 29/0653
H01L 29/407
H01L 29/66621
H01L 29/7803
H01L 29/7804
MCD main class MCM H01L 29/94 (2006.01)
MCD secondary class MCS H01L 21/76 (2006.01)
MCD additional class MCA
57 Abstract AB [EN] A semiconductor device, in which a first trench section is produced proceeding from a surface of a semiconductor body into the semiconductor body. A semiconductor layer is produced above the surface and above the first trench section. A further trench section is produced in the semiconductor layer in such a way that the first trench section and the further trench section form a continuous trench structure.
56 Cited documents identified in the search CT US000007157378B2
US020070243692A1
US020080230916A1
56 Cited documents indicated by the applicant CT
56 Cited non-patent literature identified in the search CTNP
56 Cited non-patent literature indicated by the applicant CTNP
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Search file IPC ICP H01L 21/762 T