| 54 |
Title |
TI |
[DE] Verfahren zur Passivierung einer schnellen Leistungsdiode durch eine Passivierungsschicht aus amorphem Kohlenstoff
[EN] Passivation method of a high-speed power diode by means of an amorphous carbon passivation layer
[FR] Méthode de passivation d'une diode rapide de puissance par une couche de passivation en carbone amorphe |
| 71/73 |
Applicant/owner |
PA |
SEMIKRON ELEKTRONIK GMBH, DE
|
| 72 |
Inventor |
IN |
LANG MANFRED, DE
;
LUTZ JOSEF, DE
|
| 22/96 |
Application date |
AD |
Oct 12, 1999 |
| 21 |
Application number |
AN |
99120312 |
|
Country of application |
AC |
EP |
|
Publication date |
PUB |
Feb 20, 2008 |
33
31
32 |
Priority data |
PRC
PRN
PRD |
DE
19851461
19981109
|
| 51 |
IPC main class |
ICM |
H01L 23/29
(2006.01)
|
| 51 |
IPC secondary class |
ICS |
H01L 21/314
(2006.01)
H01L 23/31
(2006.01)
H01L 29/06
(2006.01)
|
|
IPC additional class |
ICA |
|
|
IPC index class |
ICI |
|
|
Cooperative patent classification |
CPC |
H01L 21/02115
H01L 21/02274
H01L 23/291
H01L 23/3171
H01L 29/408
H01L 2924/0002
H01L 2924/13055
|
|
MCD main class |
MCM |
H01L 23/29
(2006.01)
|
|
MCD secondary class |
MCS |
H01L 21/314
(2006.01)
H01L 23/31
(2006.01)
H01L 29/06
(2006.01)
H01L 29/40
(2006.01)
|
|
MCD additional class |
MCA |
|
| 57 |
Abstract |
AB |
[EN] The passivation layer (5) of the potential ring structure (3) consists of a structured undoped oxygen-free stable hydrogenated carbon layer tempered at temperatures above 350-440o C. Power diode comprises a semiconductor body with layered zones consisting of a high ohmic middle zone (1) of first conductivity type and a second outer zone (2) of second conductivity type including a pn-junction. The two zones have a support shelf-life adjusted by irradiating with high energetic particles in two phases, and a metallic contact solderable on the cathode side. An Independent claim is also included for a process for passivating the power diode comprising: (a) producing a hydrogenated carbon layer on an oxide-free semiconductor surface by plasma deposition, where the self-bias voltage is adjusted between 700 and 1000 V and the temperature of the wafer is 140-180o C; (b) applying a photolacquer of 2-8 microns thickness to the hydrogenated carbon layer and structuring; (c) etching the hydrogenated carbon layer in an oxygen-containing plasma at a self-bias voltage of 120-500 V; (d) metallizing the thickness between 4-8 microns and structuring; and (e) tempering the wafer at 360-440o C to achieve good adhesion to the metallization. |
| 56 |
Cited documents identified in the search |
CT |
|
| 56 |
Cited documents indicated by the applicant |
CT |
|
| 56 |
Cited non-patent literature identified in the search |
CTNP |
|
| 56 |
Cited non-patent literature indicated by the applicant |
CTNP |
|
|
Citing documents |
|
Determine documents
|
|
Sequence listings |
|
|
|
Search file IPC |
ICP |
H01L 29/06 E
|
