Bibliografische Daten

Dokument US000006819089B2 (Seiten: 26)

Bibliografische Daten Dokument US000006819089B2 (Seiten: 26)
INID Kriterium Feld Inhalt
54 Titel TI [EN] Power factor correction circuit with high-voltage semiconductor component
71/73 Anmelder/Inhaber PA INFINEON TECHNOLOGIES AG, DE
72 Erfinder IN AHLERS DIRK, DE ; DEBOY GERALD, DE ; RUEB MICHAEL, AT ; STRACK HELMUT, DE ; WEBER HANS MARTIN, AT
22/96 Anmeldedatum AD 01.08.2003
21 Anmeldenummer AN 63304403
Anmeldeland AC US
Veröffentlichungsdatum PUB 16.11.2004
33
31
32
Priorität PRC
PRN
PRD
US
78602201
20011109
51 IPC-Hauptklasse ICM H01L 7/04
51 IPC-Nebenklasse ICS
IPC-Zusatzklasse ICA
IPC-Indexklasse ICI
Gemeinsame Patentklassifikation CPC H01L 29/0634
H01L 29/0696
H01L 29/1095
H01L 29/402
H01L 29/41766
H01L 29/4232
H01L 29/4236
H01L 29/4238
H01L 29/7802
H01L 29/7811
H01L 29/7825
MCD-Hauptklasse MCM
MCD-Nebenklasse MCS H01L 29/06 (2006.01)
H01L 29/78 (2006.01)
MCD-Zusatzklasse MCA H01L 29/417 (2006.01)
H01L 29/423 (2006.01)
57 Zusammenfassung AB [EN] A switching power supply including a power factor correction circuit comprises a rectifier, an inductor coupled in series with the rectifier, a semiconductor switch formed by a compensation device coupled in parallel with the rectifier and the inductor. The output circuit comprises a diode coupled in series with a capacitor both coupled in parallel with the semiconductor switch. An input current sensor, and a control unit for controlling the compensation device are provided.
56 Entgegengehaltene Patentdokumente/Zitate,
in Recherche ermittelt
CT
56 Entgegengehaltene Patentdokumente/Zitate,
vom Anmelder genannt
CT DE000004309764A1
DE000004309764C2
DE000019604043A1
DE000019604044A1
DE000019730759C1
DE000019736981C2
DE000019808348C1
DE000019823944A1
DE000019830332A1
DE000019840032C1
EP000000053854B1
EP000000069429A2
EP000000447873A2
EP000000772244A1
EP000000834926A2
EP000000939446A1
EP000000973203A2
GB000002089118A
US000003171068A
US000003925803A
US000003961356A
US000004003072A
US000004055884A
US000004072975A
US000004101922A
US000004145700A
US000004320410A
US000004345265A
US000004366495A
US000004376286A
US000004404575A
US000004417385A
US000004561003A
US000004593302A
US000004748103A
US000004754310A
US000004775881A
US000004777149A
US000004895810A
US000004914058A
US000004926226A
US000004941026A
US000004974059A
US000004975782A
US000004994871A
US000005008725A
US000005010025A
US000005019522A
US000005045903A
US000005072269A
US000005089434A
US000005126807A
US000005182234A
US000005216275A
US000005231474A
US000005283201A
US000005340315A
US000005438215A
US000005473180A
US000005559353A
US000005648283A
US000005742151A
US000005747831A
US000005801417A
US000005883411A
US000005973360A
US000006037631A
US000006307361B1
US000006388287B2
US020010050549A1
US020010053568A1
WO001997029518A1
WO001997035346A1
WO001999004437A1
WO001999023703A1
WO001999036961A1
WO001999062123A1
WO002000002250A1
WO002000014807A1
56 Entgegengehaltene Nichtpatentliteratur/Zitate,
in Recherche ermittelt
CTNP
56 Entgegengehaltene Nichtpatentliteratur/Zitate,
vom Anmelder genannt
CTNP 1998, Lorenz et al. article, "Improved MOSFET An Important Milestone Toward a New Power MOSFET Generation" featured in PCIM. 1;
1998, X.B. Chen, P.A. Mawby, K. Board et al, "Theory of a Novel Voltage-Sustaining Layer for Power Devices" (from Microelectronics Journal). 1;
1999, X.B. Chen et al. "High voltage sustaining structure with enbedded oppositely doped regions". 1;
A.S. Grove: "Physics and Technology of Semiconductor Devices" p 78-83, 1967. 1;
Academic Press, 1986, B. Jayant Baliga: "Epitaxial Silicon Technology". 1;
Article by Xing-Bi Chen presented at 2German-Chinese Electronics Week Congress, Shanghai, China, 1991. 1;
Article from Acta Electronica Sinica, Mar. 1986, "A Novel InGaAs Phototransistor by CaO Emitter" ( in Chinese) (p 35-39). 1;
B. Jayant Baliga, Sorab K. Ghandi: "Analytical Solutions for the Breakdown Voltage of Abrupt Cylindrical and Spherical Junctions" (p 739-744), 1976. 1;
B.J. Baliga, M.S. Adler, R.P. Love et al: "Insulated Gate Transistor: A New Three-Terminal MOS-Controlled Bipolar Power Device" (excerpt) (p 1394-1402), Jun. 1984. 1;
C. Frank Wheatley Jr., Gary M. Dolny: "COMFET-The Ultimate Power Device; A General Study of Power Devices" (p 121-128), Nov. 1985. 1;
Chinese Journal of Semiconductors, 1989, Chen Xingbi, Li Zhaoji, Li Zhongmin: "Breakdown Voltage of Cylindrical Boundary Abrupt Junctions" (p 463-465). 1;
Chinese Journal of Semiconductors, 1990, Li Zhoaji, Yu Hongquan, Chen Xingbi: "Temperature Distribution of Full Thermal Path of VDMOS" (p 435-440). 1;
Chinese Journal of Semiconductors, 1992, Znahg Bo, Chen Xingbi, Li Zhaoji: "Two Dimensional Electric Analysis of JTE Junctions" (p. 626-632). 1;
Chinese Journal of Semiconductors, Jul. 1998, Chen article, "Theory of a Novel Voltage Sustaining (CB) Layer for Power Devices" (from Chinese Journal of Electronics). 1;
Chinese Journal of Semiconductors, Jul. 1999, Xing Bi Chen & Johnny K. O. Sin "A Novel High Voltage Sustaining Structure with Buried Oppositely Doped Regions". 1;
Deboy et al. article, "A New Generation of High Voltage MOSFETs breaks the Limit Line of Silicon" published by IEEE (2nd, color copy added, 2nd set of Bates ranges correspond). 1;
H.R. Chang, R.D. Black, V.A.K. Temple, Wirojana Tantraporn, B. Jayant Baliga: IEEE Transaction, Nov. 1987; Self-Aligned UMOSFETS's with a Specific On-Resistance of lm cm2 (p. 2329-2334). 1;
IEDM Technical Digest excerpt (p. 239, 241), 1979. 1;
IEEE, 1977, Vinson C. Alwin, David H. Navon, Luke J. Turgeon: "Time-Dependent Carrier Flow in a Transistor Structure Under Nonisothermal Conditions" (p 1297-1304). 1;
IEEE, 1979, Adrian Rusu, Contantin Bulucea: "Deep-Depletion Breakdown Voltage of Silicon-Dioxide/Silicon MOS Capacitors"v (p 201-205). 1;
IEEE, 1979, Chenming Hu article, "Optimum Doping Profile for Minimum Ohmic Resistance and High-Breakdown Voltage". 1;
IEEE, 1979, Chenming Hu: "A Parametric Study of Power MOSFETS" (p 988-998). 1;
IEEE, 1979, J.A. Appel, H.M.J. Vacs: "High Voltage Thin Layer Devices (Resurf Devices)" (p 1384-1387). 1;
IEEE, 1980, G. Bell, W. Ladenhauf: "SIPMOS Technology, an Example of VLSI Precision Realized with Standard LSI for Power Transistors" (p 190-194). 1;
IEEE, 1980, S.C. Sun, James D. Plummer: "Modeling of the On-Resistance of LDMOS, VMDOS, and VMOS Power Transistors" (p 356-357). 1;
IEEE, 1980, Takeaki Okabe,.Isao Yoshida, Skikayuki Ochi: "A Complementary Pair of Planar-Power MOSFETS" (p 334-339). 1;
IEEE, 1980, Victor K. Temple, Robert P. Love, Peter V. Gray: "A 600-Volt MOSFET Designed for Low On-Resistance" (p 343-349). 1;
IEEE, 1980, William A. Lane, C. Andre T. Salama: "Epitaxial VVMOS Power Transistors" (p 349-355). 1;
IEEE, 1981, J.P. Stengl, H. Strack, J. Tihanyi: "Power MOS Transistors for 1000 V Blocking Voltage" (p 422-425). 1;
IEEE, 1981, Sel Colak: "Effects of Drift Region Parameters n the same properties of Power LDMOST" (p 1455-1466). 1;
IEEE, 1982, Chen and Hu article, "Optimum Doping Profile of Power MOSFET Epitaxial Layer". 1;
IEEE, 1982, Min-hwa Chi, Chenming Hu: "Some Issues of Power MOSFETS" (p 392-393). 1;
IEEE, 1983, P.L. Hower, T.M.S. Heng, C. Huang: "Optimum Design of Power MOSFETS" (p 980-984). 1;
IEEE, 1983, Victor K. Temple: "Ideal FET Doping Profile" (p 619-626). 1;
IEEE, 1983, Victor K. Temple: "Increased Avalanche Breakdown Voltge and Controlled Surface Electric Fields Using a Junction Termination Extension (JTE) Technique" (p 954-957). 1;
IEEE, 1984, Akio Nakagawa, David H. Navon: "A Time- and Temperature-Dependent 2-D Simulation of the GTO Thyristor Turn-Off Process" (p 1156-1163). 1;
IEEE, 1984, Board, Kenneth: "The Optimization of On-Resistance in Vertical DMOS Power Devices with Linear and Hexagonal Surface Geometries". 1;
IEEE, 1984, Chenming Hu, Min-Hwa Chi, Vikram M. Patel: "Optimum Designs of Power MOSFET's" (p 1693-1700). 1;
IEEE, 1985, R. Stengl, U. Gösele: "Variation of Lateral Doping-A New Concept to Avoid High Voltage Breakdown of Planar Junctions" (p 154-157). 1;
IEEE, 1986, Jerry G. Fossum, Robert J. McDonald: "Charge Control Analysis of the COMFET Turn-Off Transient" (p 1377-1382). 1;
IEEE, 1987, Wirojana Tantraporn, Victor A.K. Temple: "Multiple-Zone Single-Mask Junction Termination Extension-A High-Yield Near-Ideal Breakdown Voltage Technology" (p 220-2210). 1;
IEEE, 1987, X.B. Chen, Z.Q. Song, Z.J. Li: "Optimization of the Drift Region of Power MOSFET's with Lateral Structures and Deep Junctions" (p 2344-2350). 1;
IEEE, Apr. 1987, Daisuke Ueda, Hiromitsu Takagi, Gota Kano: An Ultra-Low On-Resistance Power MOSFET Fabricated by Using a Fully Self-Aligned Process. 1;
IEEE, Oct. 1988, Zahir Parpia, C. Andre T. Salama, Robert A. Hadaway, "A CMOS-Compatible High-Voltage IC Process" (p 1687-1694). 1;
Jul. 1998, Steve Bush, "Five-fold resistance cut for high-voltage FETs". 1;
Jul. 1999, Article "Power Semiconductors Proliferate" published in Electronics Products magazine re: Infineon CoolMOS products and IR CoolMOS- equivalent devices. 1;
Jun. 2000, Chen article, "Optimization of the Specific On-Resistance of the CoolMOS," published by IEEE Transactions on Electron Devices. 1;
Kreiger Publishing, 1987, B. Jayant Baliga: Modern Power Devices (entire text, especially excerpt, p. 182-192, 338-339). 1;
Lai, et al.; "Characteristics and Utiliazation of a New Class of Low On-Resistance MOS-Gated Power Device" (1999). 1;
Lorenz et al. article, "Drastic Reduction of On-Resistance with CoolMOS" in PCIM Europe, 1998. 1;
May 1988, Chen Xingbi, Li Zhaoji, Jiang Xu: "Two-Dimensional Numerical Analysis of High-voltage Semiconductor Electric Fields". 1;
May 1998, Article, "Siemens Introduces new Generation of High-Voltage MOSFET Technology". 1;
May 1998, Article, "Siemens' new MOSFET design drastically cuts on-state resistance". 1;
May 1998, Claus Geisler, "Birth of the Cool in MOS". 1;
Richard F. David: "Computerized Thermal Analysis of Hybrid Circuits" 27th Electronics Components Conference, May 16-18 1977 (p 324-332), 1977. 1;
Solid State Electronics, 1990, H.R. Chang, F.W. Holroyd: "High Voltage Power MOSFET's with a Trench-Gate Structure" (p 381-387). 1;
Springer Verlag, 1980, Tihanyi, "A Qualitative Study of the DC perforance of SIPMOS Transistors". 1;
Tihanyi and Krauss, SIPmOS, Elektronik 1980, p. 61-64. 1;
UMI, Dec. 1981, Richard A. Blanchard: "Optimization of Discrete High Power MOS Transistors". 1;
X.B. Chen et al., "Theory of a novel voltage-sustaining layer for power devices" (from Microelectronics Journal), 1998. 1
Zitierende Dokumente Dokumente ermitteln
Sequenzprotokoll
Prüfstoff-IPC ICP H01L 29/78